| 摘要 |
A cache controller, capable of providing an interface between a data requester and a plurality of memories including a first memory, second memory and cache memory, is configured to, in response to receiving a request 40 for data at a specified address in a specified memory: determine whether either (a) a data field in the cache memory corresponding to the specified address has been populated from the specified memory 42 or (b) the specified memory is the first memory and the data field in the cache memory has been populated from the second memory 44; and if that determination is positive, respond 43 to the request by providing the content of the corresponding data field in the cache memory. This would facilitate ROM patching. Also, a cache controller, in response to receiving a request to write data to a specified address in a specified memory (50 in Figure 5): stores the data at the specified address in the first memory, if the specified memory is the first; and if the data field in the cache memory corresponding to the specified address has not been populated from the second memory, populating that data field with the data. |
