摘要 |
一种记忆体电路,包括:一第一边缘单元,位于一记忆体之一行的一第一边界,且包括第一、第二边缘单元参考节点;以及至少一记忆体单元,每一记忆体单元包括一第一记忆体参考节点,第一边缘单元参考节点分别耦接至记忆体单元之第一记忆体参考节点;第二边缘单元参考节点作用如同记忆体单元之一第二记忆体参考节点;第一边缘单元与记忆体单元之记忆体前端片层相同,第一边缘单元具有一第一节点与第一、第二参考电压节点,第一节点连接至具有一操作电压之一电压源,并且第一接地参考电压与第二接地参考电压上之电压低于操作电压。; and at least one memory cell, each of the at least one memory cell including a first memory reference node, wherein the first edge cell reference node is coupled to respective first memory reference nodes of the at least one memory; the second edge cell reference node serves as second memory reference nodes of the at least one memory cell; front-end layers of the first edge cell are the same as front-end layers of a memory cell of the at least one memory cell, the first edge cell has a first node and first and second voltage reference nodes, the first node is coupled to a voltage source providing an operation voltage, and voltages at the first and second voltage reference nodes are lower than the operation voltage. |
申请人 |
台湾积体电路制造股份有限公司 TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
发明人 |
郑宏正 CHENG, HONG CHEN;李明怡 LEE, MING YI;潘国华 PAN, KUO HUA;陈蓉萱 CNEN, JUNG HSUAN;田丽钧 TIEN, LI CHUN;李政宏 LEE, CHENG HUNG;廖宏仁 LIAO, HUNG JEN |