发明名称 分子束磊晶生长异质磊晶低缺陷氮化镓技术;LOW THREADING DISLOCATION DENSITY GAN HETERO-EPITAXY TECHNOLOGY BY MOLECULAR BEAM EPITAXY
摘要 藉由采用奈米等级之图案化制程,氮化镓磊晶层的差排缺陷密度可以进一步降低,此归因于奈米级的磊晶结构尺寸有助于降低失配晶格累积之应变能(Strain Energy),降低缺陷的产生机率。奈米级图案化制程,皆已验证于Sapphire基板上可有效降低GaN磊晶层的差排缺陷密度。考量于大尺寸晶圆上应用的均匀性与再现性,本发明将藉由软模NIL图案化技术已成功于GaAs基板上实现InAs量子点的均匀沈积与控位。而此将进一步应用NIL技术,辅以乾式蚀刻,于异质基板上,如Si、Sapphire等,进行奈米级图案化,从而利用非平面基板来控制、沈积III-N之磊晶结构,抑制差排缺陷密度向上延伸,预期将可获致低缺陷密度。 By using nano-scale patterned process, the threading dislocation of gallium nitride epitaxy layer can be reduced. Because nano-scale epitaxy structure can reduce the strain energy, which is come from lattice mismatch, it can decrease the probability of generating defect. It is proven that the gallium nitride grown on nano-scale patterned sapphire can reduced the threading dislocation density. To transfer this method to large scale wafer with uniformity and reproducibility, it will be made by soft mask NIL patterned method. This method have been succeed to produce uniform InAs quatumn dot on GaAs substrate. Furthurmore, the nano-scale pattern is going to work on different substrate, like silicon and sapphire, with NIL technology and dry etch. Finally, we expect this technology can avoid threading dislocation grown up with epitaxy layer on non-plane substrate, so the lower defect density GaN can be produced。
申请公布号 TW201526080 申请公布日期 2015.07.01
申请号 TW102148389 申请日期 2013.12.26
申请人 国立清华大学 NATIONAL TSING HUA UNIVERSITY 发明人 郑克勇 CHENG, K. Y;王佑立 WANG, Y. L;杨伟臣 YANG, W. C;邱绍谚 CHIU, S. Y
分类号 H01L21/205(2006.01);B82Y40/00(2011.01);B82Y30/00(2011.01);C30B29/40(2006.01) 主分类号 H01L21/205(2006.01)
代理机构 代理人
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地址 新竹市光复路2段101号 TW