Systems, apparatuses, and methods for vector bit test

摘要

Systems, methods, and apparatuses for vector bit test are described. In some embodiments, a vector bit test instruction is executed to shift each packed data element of a first source by a number of bits indicated by a corresponding packed data element of a second source, and store consecutive bit values from each packed data element of the first source at the identified bit positions of a corresponding packed data element of a destination.