发明名称 シリアルインタフェース回路及びシリアル通信システム
摘要 <p><P>PROBLEM TO BE SOLVED: To improve communication efficiency in a serial interface using a plurality of lanes. <P>SOLUTION: A serial interface circuit comprises a plurality of two-way IO circuits connected to each of a plurality of lanes. Each of the two-way IO circuits can be operational as a transmission IO circuit transmitting data to a transmission lane or as a reception IO circuit receiving the data from a reception lane. A physical layer processing circuit transmits a transmission packet received from an upper layer to the transmission lane through the transmission IO circuit, and outputs a reception packet received from the reception lane through the reception IO circuit to the upper layer. Each of the lanes is usable as the transmission lane or the reception lane. The number of the transmission lanes and the number of the reception lanes are variable and controlled dynamically by a lane allocation control circuit. <P>COPYRIGHT: (C)2012,JPO&INPIT</p>
申请公布号 JP5743186(B2) 申请公布日期 2015.07.01
申请号 JP20110013484 申请日期 2011.01.25
申请人 发明人
分类号 H04L29/08;H04L29/00 主分类号 H04L29/08
代理机构 代理人
主权项
地址
您可能感兴趣的专利