Erase operation control sequencing apparatus, systems, and methods

摘要

Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate. A global select gate voltage may thereafter be enabled for application to wordline transistors coupled to the erasable memory array after a voltage applied to the substrate has reached a preselected initiation voltage level between about zero volts and an ultimate erase voltage.

主权项

1. An apparatus, comprising:
an erase initiation circuit coupled to an erasable memory array, and configured to apply a global select gate voltage to wordline transistors coupled to the erasable memory array during an erase operation after an initiation voltage has reached a preselected value that is less than an ultimate erase voltage, wherein select gates of the wordline transistors are grounded at an initial stage of the erase operation, and wherein the erasable memory array comprises a plurality of floating gate transistors.