发明名称 |
Efficient apparatus and method for testing digital shadow logic around non-logic design structures |
摘要 |
A circuit for efficiently testing digital shadow logic (504, 514) in isolation from an associated non-logic design structure (510) includes a width and delay matched bypass circuit (520) coupled to receive an n-bit input from shadow logic (504) and to generate therefrom an m-bit test output which is selectively connected to replace an m-bit output to the shadow logic (514) from the non-logic design structure (510) in a shadow logic test mode, thereby flexibly emulating the non-logic design structure to allowing separate isolated tests on the shadow logic and on the non-logic design structure. |
申请公布号 |
US9069042(B2) |
申请公布日期 |
2015.06.30 |
申请号 |
US201314072295 |
申请日期 |
2013.11.05 |
申请人 |
Freescale Semiconductor, Inc. |
发明人 |
Raina Rajesh;Abadir Magdy S.;Carder Darrell L. |
分类号 |
G01R31/28;G01R31/3177 |
主分类号 |
G01R31/28 |
代理机构 |
Terrile, Cannatti, Chambers & Holland, LLP |
代理人 |
Terrile, Cannatti, Chambers & Holland, LLP ;Cannatti Michael Rocco |
主权项 |
1. A semiconductor device, comprising:
a non-logic circuit block coupled to receive an n-bit input and to generate an m-bit output from the n-bit input after a first propagation delay; a shadow logic coupled to the non-logic circuit block for interfacing the non-logic circuit block with external circuitry by generating an n-bit input signal for selective connection to the n-bit input of the non-logic circuit block and by processing an m-bit output signal that may be selectively connected from the m-bit output of the non-logic circuit block to generate a shadow logic output; a test input control circuit for generating a multi-bit input test signal for the shadow logic with each bit of the multi-bit input test signal being independently controllable; a bypass circuit coupled to receive the n-bit input in a shadow logic test mode and to generate an m-bit test output from the n-bit input with each bit of the m-bit test output from the bypass circuit being independently controllable, where the bypass circuit comprises delay matching circuitry for matching the first propagation delay of the non-logic circuit block; and a signal selection circuit coupled to the non-logic circuit block, bypass circuit, and shadow logic for selectively passing the m-bit output to the shadow logic in a first mode and passing the m-bit test output to the shadow logic in the shadow logic test mode. |
地址 |
Austin TX US |