发明名称 |
Package substrate, method of manufacturing the package substrate and semiconductor package including the package substrate |
摘要 |
A package substrate may include an insulating substrate, a first land array, a second land array, a first plating line and a second plating line. The first land array may be arranged on a first surface of the insulating substrate. The second land array may be arranged on a second surface of the insulating substrate opposite to the first surface. The second land array may be electrically connected to the first land array. The second land array may include outer lands and inner lands. The first plating line may be connected to the outer lands. The second plating line may be connected between the outer lands and the inner lands. The second plating line may have a width narrower than that of the first plating line. The second plating line may be removed by applying a removing current to the first plating line prior to the first plating line. |
申请公布号 |
US9072188(B2) |
申请公布日期 |
2015.06.30 |
申请号 |
US201414194647 |
申请日期 |
2014.02.28 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
Yoon Tae-Young |
分类号 |
H05K1/11;H05K3/24;H01L25/065;H01L23/48;H01L23/498;H01L23/538;H01L23/31;H01L23/00 |
主分类号 |
H05K1/11 |
代理机构 |
Renaissance IP Law Group LLP |
代理人 |
Renaissance IP Law Group LLP |
主权项 |
1. A package substrate comprising:
an insulating substrate; a first land array arranged on a first surface of the insulating substrate; a second land array arranged on a second surface of the insulating substrate opposite to the first surface and electrically connected to the first land array, the second land array including outer lands and inner lands; a first plating line connected to the outer lands; and a second plating line disposed between the outer lands and the inner lands, the second plating line having a width narrower than that of the first plating line, wherein the second plating line is configured to be removed by a removing current, which is supplied through the first plating line. |
地址 |
KR |