发明名称 Semiconductor device and driving method thereof
摘要 The circuit includes a first wiring for supplying a power supply potential to a signal processing circuit, a transistor for controlling electrical connection between the first wiring and a second wiring for supplying the a power supply potential, and a transistor for determining whether or not the first wiring is grounded. At least one of the two transistors is a transistor whose channel is formed in the oxide semiconductor layer. This makes it possible to reduce power consumption due to cutoff current of at least one of the two transistors.
申请公布号 US9070776(B2) 申请公布日期 2015.06.30
申请号 US201213442995 申请日期 2012.04.10
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 Kobayashi Hidetomo
分类号 G11C5/14;H01L29/786;H01L27/12 主分类号 G11C5/14
代理机构 Fish & Richardson P.C. 代理人 Fish & Richardson P.C.
主权项 1. A semiconductor device comprising: a power supply control circuit comprising a first transistor, a second transistor, a third transistor, and a fourth transistor; and a signal processing circuit comprising an input terminal and an output terminal, wherein a gate of the first transistor is electrically connected to one of a source and a drain of the first transistor, wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor and one of a source and a drain of the third transistor, wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the fourth transistor and the input terminal, wherein the other of the source and the drain of the second transistor is electrically connected to a first wiring, wherein a gate of the third transistor is electrically connected to a gate of the fourth transistor and the output terminal, wherein the other of the source and the drain of the third transistor and the other of the source and the drain of the fourth transistor is electrically connected to a second wiring, and wherein at least one of the second transistor and the fourth transistor comprises a channel included in an oxide semiconductor layer.
地址 Atsugi-shi, Kanagawa-ken JP