| 发明名称 | Non-volatile memory system with reset verification mechanism and method of operation thereof | ||
| 摘要 | A method of operation of a non-volatile memory system includes: providing a resistive storage element having a high resistance state and a low resistance state; coupling an analog multiplexer to the resistive storage element for applying a bias voltage; and switching between a verification bias and a read bias through the analog multiplexer for increasing a read margin between the high resistance state and the low resistance state. | ||
| 申请公布号 | US9070441(B2) | 申请公布日期 | 2015.06.30 |
| 申请号 | US201213723965 | 申请日期 | 2012.12.21 |
| 申请人 | Sony Corporation | 发明人 | Otsuka Wataru;Sumino Jun;Tsushima Tomohito;Kitagawa Makoto;Kunihiro Takafumi |
| 分类号 | G11C13/00;H01L45/00 | 主分类号 | G11C13/00 |
| 代理机构 | Ishimaru & Associates LLP | 代理人 | Ishimaru & Associates LLP |
| 主权项 | 1. A method of operation of a non-volatile memory system comprising: providing a resistive storage element having a high resistance state and a low resistance state; coupling an analog multiplexer to the resistive storage element for applying a bias voltage; and switching between a verification bias and a read bias through the analog multiplexer for increasing a read margin between the high resistance state and the low resistance state including asserting a well switch for referencing the bias voltage to a well voltage. | ||
| 地址 | Tokyo JP | ||