发明名称 |
Source device, communication system, method of controlling source device, and method of controlling sink device |
摘要 |
A source device includes: a low-speed data supply section configured to supply, as low-speed data, data generated in synchronization with a low clock signal out of clock signals having different frequencies, the low clock signal having a frequency lower than a predetermined value; a high-speed data supply section configured to supply, as high-speed data, data generated in synchronization with a high clock signal out of the clock signals, the high clock signal having a frequency higher than that of the low clock signal; a dividing section configured to divide the low-speed data into a predetermined number of pieces of data in accordance with a ratio between the frequencies of the high and low clock signals; and a data transmitting section configured to store the high-speed data and the divided pieces of low-speed data in data having a predetermined data size, and to transmit the stored data. |
申请公布号 |
US9069490(B2) |
申请公布日期 |
2015.06.30 |
申请号 |
US201414153252 |
申请日期 |
2014.01.13 |
申请人 |
Sony Corporation |
发明人 |
Morikawa Keiji;Kametani Satoshi;Imai Makoto;Nishimoto Kazumasa |
分类号 |
G06F1/12 |
主分类号 |
G06F1/12 |
代理机构 |
Wolf, Greenfield & Sacks, P.C. |
代理人 |
Wolf, Greenfield & Sacks, P.C. |
主权项 |
1. A source device comprising:
a low-speed data supply section configured to supply, as low-speed data, data generated in synchronization with a low clock signal out of a plurality of clock signals having different frequencies, the low clock signal having a frequency that is lower than a predetermined value; a high-speed data supply section configured to supply, as high-speed data, data generated in synchronization with a high clock signal out of the plurality of clock signals, the high clock signal having a frequency that is higher than the frequency of the low clock signal; a dividing section configured to divide the low-speed data into a predetermined number of pieces of data, the predetermined number being in accordance with a ratio of the frequency of the high clock signal with respect to the frequency of the low clock signal; and a data transmitting section configured to store the high-speed data and the divided pieces of low-speed data in data having a predetermined data size, and to transmit the stored high-speed data and divided pieces of low-speed data. |
地址 |
Tokyo JP |