Concurrent page table walker control for TLB miss handling

摘要

In an embodiment, a page miss handler includes paging caches and a first walker to receive a first linear address portion and to obtain a corresponding portion of a physical address from a paging structure, a second walker to operate concurrently with the first walker, and a logic to prevent the first walker from storing the obtained physical address portion in a paging cache responsive to the first linear address portion matching a corresponding linear address portion of a concurrent paging structure access by the second walker. Other embodiments are described and claimed.

主权项

1. A processor comprising:
at least one execution unit to execute instructions; and a page miss handler including a plurality of paging caches and a first walker structure to receive, responsive to a miss in a translation lookaside buffer (TLB) of the processor, at least a portion of a first linear address and to obtain a corresponding portion of a physical address from one or more paging structures stored in a system memory, a second walker structure to operate concurrently with the first walker structure, and a concurrent walker logic to prevent the first walker structure from storing the obtained physical address portion in one of the paging caches responsive to the first linear address portion matching a corresponding linear address portion of a concurrent paging structure access by the second walker structure, wherein the first walker structure is to access a first paging structure using a first segment of the first linear address portion and a value of a control register and to store a first accessed entry from the first paging structure in a first paging cache, based on a state of a first field of a status register associated with the first walker structure and to access a second paging structure using the first accessed entry and a second segment of the first linear address portion and to store a second accessed entry from the second paging structure in a second paging cache, based on a state of a second field of the status register associated with the first walker structure.