发明名称 |
Self evaluation of system on a chip with multiple cores |
摘要 |
A method and structure tests a system on a chip (SoC) or other integrated circuit having multiple cores for chip characterization to produce a partial good status. A Self Evaluation Engine (SEE) on each core creates a quality metric or partial good value for the core. The SEE executes one or more tests to create a characterization signature for the core. The SEE then compares the characterization signature of a core with a characterization signature of neighboring cores to determine the partial good value for the core. The SEE may output a result to create a full characterization map for detailed diagnostics or a partial good map with values for all cores to produce a partial good status for the entire SoC. |
申请公布号 |
US9069041(B2) |
申请公布日期 |
2015.06.30 |
申请号 |
US201213705353 |
申请日期 |
2012.12.05 |
申请人 |
International Business Machines Corporation |
发明人 |
Douskey Steven M.;Fitch Ryan A.;Hamilton Michael J.;Kaufer Amanda R. |
分类号 |
G01R31/28;G01R31/317;G01R31/3177 |
主分类号 |
G01R31/28 |
代理机构 |
Martin & Associates, LLC |
代理人 |
Martin & Associates, LLC ;Petersen Bret J. |
主权项 |
1. An integrated circuit comprising:
a plurality of cores wherein each of the plurality of cores is considered a local core with a plurality of neighboring cores, wherein each local core further comprises:
a self test mechanism that executes at least one test on the local core and produces a local signature for the local core where the local signature characterizes the local core; anda self evaluation engine (SEE) that compares the local signature with a plurality of neighbor core signatures produced by the plurality of neighboring cores to determine a goodness value for the local core. |
地址 |
Armonk NY US |