| 发明名称 |
SEMICONDUCTOR MANUFACTURING USING DESIGN VERIFICATION WITH MARKERS |
| 摘要 |
A first circuit design is entered in an electronic design automation (EDA) computer system. The first circuit design includes a first feature with a first node. A marker is associated with the first node and represents a voltage associated with the first node as an algebraic expression of a numerical value representing a property of the circuit design. The marker is used to determine if the component of the circuit design violates a design rule. |
| 申请公布号 |
US2015178438(A1) |
申请公布日期 |
2015.06.25 |
| 申请号 |
US201314137530 |
申请日期 |
2013.12.20 |
| 申请人 |
DEMIRCAN ERTUGRUL;Reber Douglas M.;Stockinger Michael A.;Travis Edward O. |
发明人 |
DEMIRCAN ERTUGRUL;Reber Douglas M.;Stockinger Michael A.;Travis Edward O. |
| 分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method comprising:
entering a first circuit design in an electronic design automation (EDA) computer system, wherein the first circuit design includes a first feature with a first node; providing a marker that represents a voltage associated with the first node as an algebraic expression of a first numerical value, wherein the first numerical value represents a property of the first circuit design; and using the marker for a determination if the first feature of the first circuit design causes a design rule violation. |
| 地址 |
Austin TX US |
