发明名称 |
COMMUNICATION DEVICE, COMMUNICATION SYSTEM, AND SYNCHRONOUS CONTROL METHOD |
摘要 |
A communication device includes a transmission port and a reception port communicating with other network units, a system bus I/F unit communicating with a synchronous target, n (n is an integer of 2 or more) delay counters counting a predetermined period of time, a delay-counter control unit that, upon receiving a synchronous packet input with a predetermined cycle from the reception port, causes the delay counters to count a cycle that is n times as long as the predetermined cycle and controls the delay counters such that counts of the delay counters are cleared at different timings, and a synchronous-pulse output unit outputting a synchronous pulse to the synchronous target through the system bus I/F unit when there is the counter whose count value after being cleared becomes equal to a synchronous-pulse output value. |
申请公布号 |
US2015180598(A1) |
申请公布日期 |
2015.06.25 |
申请号 |
US201214406574 |
申请日期 |
2012.08.01 |
申请人 |
Arakawa Satoshi |
发明人 |
Arakawa Satoshi |
分类号 |
H04J3/06;G05B15/02;H04L7/04 |
主分类号 |
H04J3/06 |
代理机构 |
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代理人 |
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主权项 |
1. A communication device comprising:
a first communication unit that communicates with another communication device; a second communication unit that communicates with a synchronous target; n (n is an integer of 2 or more) counters that count a predetermined period of time; a counter control unit that, upon receiving a synchronous packet input with a predetermined cycle from the first communication unit, causes the counters to count a cycle that is n times as long as the predetermined cycle and controls the counters such that counts of the counters are cleared at different timings; and a synchronous-pulse output unit that outputs a synchronous pulse to the synchronous target through the second communication unit when there is a counter whose count value after being cleared becomes equal to a synchronous-pulse output value. |
地址 |
Tokyo JP |