CACHE MEMORY DATA COMPRESSION AND DECOMPRESSION

摘要

A cache memory data compression and decompression technique is described. A processor device includes a memory controller unit (MCU) coupled to a main memory and a cache memory. The MCU includes a cache memory data compression and decompression module that compresses data received from the main memory. The compressed data may then be stored in the cache memory. The cache memory data compression and decompression module may also decompress data that is stored in the cache memory. For example, in response to a cache hit for data requested by a processor, the compressed data in the cache memory may be decompressed and subsequently read or operated upon by the processor.

主权项

1. A processor comprising:
a cache memory; a memory channel coupled to a main memory; and a memory controller unit (MCU) coupled to the cache memory and the memory channel, wherein the MCU comprises a cache memory data compression and decompression (CMDCD) module comprising:
a cache memory data compression function block operable to:
receive a cache line from the main memory over the memory channel;split the cache line into a first portion of data blocks and a second portion of data blocks;compress a first data block of the first portion into a first compressed data block based on matching contents of the first data block with contents of other data blocks from the same first portion;compress a second data block of the second portion into a second compressed data block based on matching contents of the second data block with contents of other data blocks from the same second portion; andstore the first portion comprising the first compressed data block and the second portion comprising the second compressed data block in the cache memory.