发明名称 |
GATE FORMATION MEMORY BY PLANARIZATION |
摘要 |
Semiconductor devices and methods of producing the devices are disclosed. The devices are formed by forming a gate structure on a substrate. The gate structure includes a charge trapping dielectric formed between the substrate and a first poly layer. A top dielectric is formed over the poly layer and a sidewall dielectric is formed on a side of the poly layer. A second poly layer is formed over the gate structure such that a portion of the second poly layer includes a vertical portion that is in contact with the sidewall dielectric and a top portion that is in contact with the top dielectric. The top portion of the second poly layer can then be removed through, for instance, planarization. |
申请公布号 |
WO2015095717(A1) |
申请公布日期 |
2015.06.25 |
申请号 |
WO2014US71524 |
申请日期 |
2014.12.19 |
申请人 |
SPANSION LLC |
发明人 |
FANG, SHENQING;CHEN, CHUN;MATSUMOTO, DAVID;RAMSBEY, MARK, T. |
分类号 |
H01L21/8247;H01L27/115 |
主分类号 |
H01L21/8247 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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