Methods to Characterize an Embedded Interface of a CMOS Gate Stack

摘要

Metal gate high-k capacitor structures with lithography patterning are used to extract gate work function using a combinatorial workflow. Oxide terracing, together with high productivity combinatorial process flow for metal deposition can provide optimum high-k gate dielectric and metal gate solutions for high performance logic transistors. Surface treatments can be inserted at three possible steps during the formation of the MOSCAP structures. The high productivity combinatorial technique can provide an evaluation of effective work function for given high-k dielectric metal gate stacks for PMOS and NMOS transistors, which is critical in identifying and selecting the right materials.

主权项

1. A method for screening gate stacks, the method comprising providing a semiconductor substrate;
forming a first oxide layer on the substrate; defining a plurality of site-isolated regions (SIRs) on the first oxide layer; patterning the first oxide layer in each SIR to form an active area on a surface of the substrate within each SIR; applying a first surface treatment to at least one of the SIRs; forming a second oxide layer on the treated active area within each SIR; etching the second oxide layer within each SIR, wherein a thickness of the second oxide layer is varied in a combinatorial manner; forming a high-k dielectric layer on the second oxide layer within each SIR; forming a metal layer on the high-k dielectric layer within each SIR; patterning the metal layer to form metal electrodes, wherein the metal electrode, the high-k dielectric layer, and the substrate form a capacitor device within the active area of each SIR; and measuring an electrical parameter of the capacitor device formed within each SIR; wherein the first surface treatment is applied to at least one of the active area, the second oxide layer after the etching, or the high-k dielectric layer.