发明名称 THERMAL ANALYSIS FOR TIERED SEMICONDUCTOR STRUCTURE
摘要 Among other things, one or more systems and techniques for analyzing a tiered semiconductor structure are provided. One or more segments are defined for the tiered semiconductor structure. The one or more segments are iteratively evaluated during electrical simulation while taking into account thermal properties to determine power metrics for the segments. The power metrics are used to determine temperatures generated by integrated circuitry within the segments. Responsive to a segment having a temperature above a temperature threshold, a temperature action plan, such as providing an alert or inserting one or more thermal release structures into the segment, is implemented. In this way, the one or more segments are iteratively evaluated to identify and resolve thermal and reliability issues.
申请公布号 US2015179529(A1) 申请公布日期 2015.06.25
申请号 US201314133840 申请日期 2013.12.19
申请人 Taiwan Semiconductor Manufacturing Company Limited 发明人 Chen Chih-Liang;Tzeng Jiann-Tyng;Sung Shu-Hui;Young Charles Chew-Yuen
分类号 H01L21/66;G01N25/72 主分类号 H01L21/66
代理机构 代理人
主权项 1. A method for analyzing a tiered semiconductor structure, comprising: defining one or more segments for a tiered semiconductor structure, the one or more segments comprising a first segment; determining a set of thermal properties for the first segment; performing electrical analysis on the first segment based upon at least one of an initial temperature or a time period to obtain a first power metric; determining a new temperature for the first segment based upon the first power metric and the set of thermal properties; and utilizing the new temperature to determine a thermal analysis characteristic for the first segment.
地址 Hsin-Chu TW