发明名称 |
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE |
摘要 |
An object is to provide a semiconductor device in which defects are reduced and miniaturization is achieved while favorable characteristics are maintained. A semiconductor layer is formed; a first conductive layer is formed over the semiconductor layer; the first conductive layer is etched with use of a first resist mask to form a second conductive layer having a recessed portion; the first resist mask is reduced in size to form a second resist mask; the second conductive layer is etched with use of the second resist mask to form source and drain electrodes each having a projecting portion with a tapered shape at the peripheries; a gate insulating layer is formed over the source and drain electrodes to be in contact with part of the semiconductor layer; and a gate electrode is formed in a portion over the gate insulating layer and overlapping with the semiconductor layer. |
申请公布号 |
US2015179775(A1) |
申请公布日期 |
2015.06.25 |
申请号 |
US201514626176 |
申请日期 |
2015.02.19 |
申请人 |
Semiconductor Energy Laboratory Co., Ltd. |
发明人 |
SASAGAWA Shinya;KURATA Motomu |
分类号 |
H01L29/66;H01L21/441 |
主分类号 |
H01L29/66 |
代理机构 |
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代理人 |
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主权项 |
1. A method for manufacturing a semiconductor device comprising the steps of:
forming a semiconductor layer; forming a first conductive layer of a single layer over the semiconductor layer; forming a first resist mask with use of light with a wavelength less than or equal to 365 nm over the first conductive layer; etching the first conductive layer with use of the first resist mask to form a second conductive layer having a recessed portion; reducing the first resist mask in size to form a second resist mask; etching the second conductive layer with use of the second resist mask to form a source electrode and a drain electrode each having a projecting portion with a tapered shape at peripheries of the source electrode and the drain electrode; forming a gate insulating layer over the source electrode and the drain electrode and in contact with a part of the semiconductor layer; and forming a gate electrode in a portion which is over the gate insulating layer and overlaps with the semiconductor layer. |
地址 |
Atsugi-shi JP |