CLOCK ASSIGNMENTS FOR PROGRAMMABLE LOGIC DEVICE

摘要

Various techniques are provided to perform clock assignments in a programmable logic device (PLD). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a programmable logic device (PLD), synthesizing the design into a plurality of components of the PLD configured to perform the operations, and performing a simulated annealing process to determine a layout of the components in the PLD based on a system cost including a clock assignment cost for global clock signals of the PLD. Additional methods, systems, machine-readable mediums, and other techniques are also provided.

主权项

1. A computer-implemented method comprising:
receiving a design identifying operations to be performed by a programmable logic device (PLD); synthesizing the design into a plurality of components of the PLD configured to perform the operations; and performing a simulated annealing process to determine a layout of the components in the PLD based on a system cost including a clock assignment cost for global clock signals of the PLD.