发明名称 HIGH VOLTAGE DEPLETION MODE N-CHANNEL JFET
摘要 An integrated circuit and method having a JFET with a buried drift layer and a buried channel in which the buried channel is formed by implanting through segmented implant areas so that the doping density of the buried channel is between 25 percent and 50 percent of the doping density of the buried drift layer.
申请公布号 US2015179452(A1) 申请公布日期 2015.06.25
申请号 US201414572936 申请日期 2014.12.17
申请人 Texas Instruments Incorporated 发明人 HOWER Philip Leland;PENDHARKAR Sameer;DENISON Marie
分类号 H01L21/225;H01L21/266;H01L29/06;H01L27/098;H01L21/8232 主分类号 H01L21/225
代理机构 代理人
主权项 1. An integrated circuit, comprising: a substrate, the substrate having a first conductivity type; an epitaxial layer on the substrate, the epitaxial layer having the conductivity type of the substrate; a junction field effect transistor (JFET), the JFET including: a buried drift layer in the substrate and the epitaxial layer so that a top surface of the buried drift layer is below a top surface of the epitaxial layer, the buried drift layer having an opposite conductivity type from the substrate, the buried drift layer having a channel end and a drain end;a buried channel in the substrate and the epitaxial layer abutting the channel end of the buried drift layer, the buried channel having the conductivity type of the buried drift layer, the buried channel having an average doping density in the buried channel between 25 percent and 50 percent of an average doping density in the buried drift layer and an average thickness between 75 percent and 100 percent of an average thickness of the buried drift layer;a gate in the epitaxial layer above the buried channel;a drain well in the epitaxial layer extending to the drain end of the buried drift layer, the drain well having the conductivity type of the buried drift layer; anda source well in the epitaxial layer adjacent to the gate opposite from the drain well, the source well having the conductivity type of the buried drift layer.
地址 Dallas TX US