APPARATUS AND METHOD FOR EXTENDED CACHE CORRECTION

摘要

An apparatus includes a semiconductor fuse array, a cache memory, and a plurality of cores. The semiconductor fuse array is disposed on a die, into which is programmed the configuration data. The semiconductor fuse array has a first plurality of semiconductor fuses that is configured to store compressed cache correction data. The a cache memory is disposed on the die. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the semiconductor fuse array and the cache memory, and is configured to access the semiconductor fuse array upon power-up/reset, to decompress the compressed cache correction data, and to distribute decompressed cached correction data to initialize the cache memory.

主权项

1. An apparatus for providing configuration data to an integrated circuit, the apparatus comprising:
a semiconductor fuse array, disposed on a die, into which is programmed the configuration data, said semiconductor fuse array comprising:
a first plurality of semiconductor fuses, configured to store compressed cache correction data; a cache memory, disposed on said die; and a plurality of cores, disposed on said die, wherein each of said plurality of cores is coupled to said semiconductor fuse array and said cache memory, and is configured to access said semiconductor fuse array upon power-up/reset, to decompress said compressed cache correction data, and to distribute decompressed cached correction data to initialize said cache memory.