发明名称 Multiple Execution Unit Processor Core
摘要 A processor core includes multiple execution units, such as a first execution unit and a second execution unit. The first execution unit may include a first functional component that supports a superscalar pipeline. The second execution unit may include a second functional component supporting a scalar pipeline. The processor core may operate in a high-performance mode by using the first execution unit and powering down the second execution unit and operate in a low-power mode by using the second execution unit and powering down the first execution unit. The processor core may include common elements shared between the multiple execution units, such as a common instruction cache, data cache, register file(s), and more.
申请公布号 US2015177821(A1) 申请公布日期 2015.06.25
申请号 US201414202910 申请日期 2014.03.10
申请人 Broadcom Corporation 发明人 Senthinathan Ramesh;Yeager Kenneth;Leonard Jason Alexander;O'Donnell Lief;Belhazy Michael
分类号 G06F1/32;G06F9/30 主分类号 G06F1/32
代理机构 代理人
主权项 1. A system comprising: a processor core comprising: a first execution unit within the processor core; anda second execution unit within the processor core, the second execution unit different from the first execution unit; and where the processor core is configured to: operate in a first mode by using the first execution unit and powering down the second execution unit; and operate in a second mode by using the second execution unit and powering down the first execution unit.
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