DATA TRANSFER BETWEEN CLOCK DOMAINS

摘要

A system (1) for transferring a data signal (sig_fast) from a first clock domain (4) to a second clock domain (8). The first clock domain (4) has a first clock (ck_fast) with a frequency greater than the frequency of a second clock (ck_slow) in the second clock domain (8). The system (1) also has a signal input (10) for receiving an input signal (sig_fast) from the first clock domain (4), means (16, 18) for checking whether the second clock (ck_slow) is in a part of its cycle away from a forthcoming transition, and means (22) for transferring the input signal (sig_fast) to the second clock domain (8) if the checking means (16, 18) determines that the second clock (ck_slow) is in part of its cycle away from a forthcoming transition. The checking means (16, 18) are clocked by the first clock (ck_fast).

主权项

1. A system for transferring a data signal from a first clock domain to a second clock domain, wherein the first clock domain comprises a first clock having a frequency greater than a frequency of a second clock in the second clock domain, the system comprising:
a signal input for receiving an input signal from the first clock domain; a checking circuit portion for checking whether the second clock is in a part of its cycle away from a forthcoming transition, said checking circuit portion being clocked by the first clock; and a transferring circuit portion for transferring the input signal to the second clock domain if the checking circuit portion determines that the second clock is in part of its cycle away from a forthcoming transition.