发明名称 |
AUTOMATIC TEST-PATTERN GENERATION FOR MEMORY-SHADOW-LOGIC TESTING |
摘要 |
An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode. |
申请公布号 |
US2015179282(A1) |
申请公布日期 |
2015.06.25 |
申请号 |
US201514640601 |
申请日期 |
2015.03.06 |
申请人 |
STMicroelectronics International N.V. |
发明人 |
Kohli Nishu |
分类号 |
G11C29/10 |
主分类号 |
G11C29/10 |
代理机构 |
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代理人 |
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主权项 |
1. A method for automated test pattern generation (ATPG), the method comprising the step of generating a test pattern using respective ATPG memory address locations of a memory coupled to a logic circuit under test. |
地址 |
Amsterdam NL |