Method For Integrated Circuit Patterning

摘要

A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a first spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The plurality of lines is removed, thereby providing a patterned first spacer layer over the substrate. The method further includes forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto sidewalls of the patterned first spacer layer, and forming a patterned material layer over the second spacer layer with a second mask. Whereby, the patterned material layer and the second spacer layer collectively define a plurality of trenches.

主权项

1. A method of forming a target pattern for an integrated circuit, the method comprising:
forming a plurality of lines over a substrate with a first mask; forming a first spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines; removing at least a portion of the first spacer layer to expose the plurality of lines; removing the plurality of lines thereby providing a patterned first spacer layer over the substrate; forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto sidewalls of the patterned first spacer layer; and forming a patterned material layer over the second spacer layer with a second mask, whereby the patterned material layer and the second spacer layer collectively define a plurality of trenches, and wherein the second spacer layer remains formed over the patterned first spacer layer and on the sidewalls of the patterned first spacer layer after the plurality of trenches are defined.