STACKED MULTIPLE-INPUT DELAY GATES

摘要

Embodiments of the present invention disclose a method, program product, and a logic circuit structure for correcting early-mode timing violations in a digital circuit design. A portion of a digital circuit design is identified having an early-mode timing violation. A logic circuit is identified within the identified portion of a digital circuit design having the early-mode timing violation. At least one input of the identified logic circuit is identified as having the early-mode timing violation. At least one transistor is added to the identified logic circuit, wherein the input of the added at least one transistor is coupled to the identified at least one input of the identified logic circuit, and wherein the addition of the at least one transistor delays the signal received at the identified at least one input to eliminate the early-mode timing violation.

主权项

1. A method of correcting early-mode timing violations in a digital circuit design, the method comprising:
performing, by one or more computer processors, logic synthesis of a digital circuit design to create a netlist, wherein the netlist includes a portion of the digital circuit design having an early-mode timing violation; identifying, by one or more computer processors, the portion of the digital circuit design having the early-mode timing violation; identifying, by one or more computer processors, a first logic circuit within the identified portion having the early-mode timing violation; identifying, by one or more computer processors, at least one input of the first logic circuit having the early-mode timing violation; replacing, by one or more processors, the first logic circuit with an alternative logic circuit in the digital circuit design, wherein, when compared to the first logic circuit, the alternative logic circuit includes at least one additional transistor connected in series on one or both of a PMOS side and an NMOS side of the alternative logic circuit, and wherein the alternative logic circuit is configured to utilize the least one additional transistor to delay a signal received at an input of the an alternative logic circuit to eliminate the early-mode timing violation; and manufacturing a circuit based, at least in part, on the digital circuit design.