| 摘要 |
An audio system comprises a master device, a slave device accessory and a wired connection including at least a first wire for transmitting master clock data signals to the slave and a second wire for transferring data between the devices in half-duplex fashion. In order to compensate for a round-trip transmission delay, the slave transmits a synchronisation data pattern on the second wire, wherein the synchronisation data pattern comprises signal level transitions at timings that are based on the received master clock signal and an initial delay value stored in the slave (tds, fig. 22). The master determines whether the timings of the received signal level transitions are early or late, and transmits timing delay control data on the second wire based on the determination. The slave updates the stored delay value and the process is repeated to converge on a delay value such that the total round trip delay equals one bit period. |
