| 摘要 |
An apparatus comprises hardware logic arranged to normalise, or renormalize, an n-bit input number, where the hardware logic comprises: a leading zero counter 204 arranged to compute a number of leading zeroes in the n-bit number; and left shifting logic 206-210 arranged to perform left shifting of the n-bit number, where at least a portion of the left shifting is performed in parallel with the computing of the number of leading zeroes. The left shifting and the leading zero count may be performed independently in a fully parallel implementation 201. Alternatively a subset of the bits output by a leading zero counter may be input to a left shifter 208 and the output from the left shifter then input to a renormalisation block 210 which completes the remainder of the left shifting operation independently of any further input from the leading zero counter, in a partially parallel or hybrid implementation 202. The renormaliser block may comprise a tree of logic elements (Figure 5 for example). |
