Clock signal synchronization

摘要

Circuits and methods are introduced to allow for timing relationship between a clock signal (Clock) and a synchronization signal (Sync) to be observed. The observations may include observing the timing relationship between a capture edge of the clock signal and a transition of the synchronization signal. Based on the observations the timing (OUT1, OUT2, OUT3) of the synchronization signal transition may be adjusted (CNTRL). Observing the timing relationship (OUT1, OUT2, OUT3) may include providing a delayed synchronization signal (SYNCP) and a delayed clock signal (CLOCKP). The delayed synchronization signal may provide what happens before the capture edge of the clock signal. The delayed clock signal may provide what happens after the capture edge of the clock signal.