发明名称 Memory controller method and system compensating for memory cell data losses
摘要 A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing row addresses identifying rows containing DRAM memory cells that are likely to lose data during normal refresh of the memory cells. Upon power-up, the data from the non-volatile memory are transferred to a comparator in the memory controller. The comparator compares the row addresses to row addresses from a refresh shadow counter that identify the rows in the DRAMs being refreshed. When a row of memory cells is being refreshed that is located one-half of the rows away from a row that is likely to loose data, the memory controller causes the row that is likely to loose data to be refreshed. The memory controller also includes error checking circuitry for identifying the rows of memory cells that are likely to lose data during refresh.
申请公布号 US9064600(B2) 申请公布日期 2015.06.23
申请号 US201414189607 申请日期 2014.02.25
申请人 Micron Technology, Inc. 发明人 Klein Dean A.
分类号 G11C29/00;H03M13/00;G11C11/406;G11C7/20;G11C11/4072;G11C29/08 主分类号 G11C29/00
代理机构 Dorsey & Whitney LLP 代理人 Dorsey & Whitney LLP
主权项 1. An apparatus, comprising: a memory module, including: a memory device; anda data record configured to store in the memory module identifying information corresponding to memory cells in the memory device having relatively weak data retention characteristics; and a memory controller coupled to the memory module, the memory controller configured to transfer at least some of the identifying information from the memory module to the memory controller, the memory controller further configured to invert a most significant bit of an address to be refreshed, compare the address to be refreshed with the inverted most significant bit to identifying information, and apply signals to the memory module that cause memory cells in the memory device having relatively weak data retention characteristics to be refreshed at a rate that is faster than a rate at which other memory cells in the memory device are refreshed based on the comparison of the address to be refreshed with the inverted most significant bit to the identifying information indicating a match.
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