发明名称 |
Electro-optical display device and display method thereof |
摘要 |
A method of reducing power consumption of an electro-optical display device which can display a still image with the use of analog signals. A circuit in which a small amount of leakage current flows between a source and a drain of a selection transistor when the selection transistor is off; the source of the selection transistor is connected to a gate of an N-channel driving transistor, a gate of a P-channel driving transistor, and one electrode of a capacitor; and a source of each of the N-channel driving transistor and the P-channel driving transistor is connected to one electrode of a display element is provided in each pixel. The longest time of one frame is set to 100 seconds or longer with the use of such a circuit, whereby power consumption at the time of rewriting is reduced. |
申请公布号 |
US9064473(B2) |
申请公布日期 |
2015.06.23 |
申请号 |
US201113100803 |
申请日期 |
2011.05.04 |
申请人 |
Semiconductor Energy Laboratory Co., Ltd. |
发明人 |
Takemura Yasuhiko |
分类号 |
G09G3/36;G02F1/1362;H01L27/12;H01L29/786;G02F1/136;G02F1/137;H04N13/04 |
主分类号 |
G09G3/36 |
代理机构 |
Robinson Intellectual Property Law Office, P.C. |
代理人 |
Robinson Eric J.;Robinson Intellectual Property Law Office, P.C. |
主权项 |
1. An electro-optical display device comprising a pixel, the pixel comprising:
a first transistor comprising a channel formation region in an oxide semiconductor layer; a second transistor; a third transistor; a capacitor; and a display element, wherein a source of the first transistor is directly connected to a gate of the second transistor, a gate of the third transistor, and one electrode of the capacitor, wherein the display element comprises a first electrode and a second electrode, wherein a source of the second transistor and a source of the third transistor are directly connected to the first electrode of the display element, wherein a drain of the third transistor is connected to a low potential line, wherein the second transistor is an N-channel transistor and the third transistor is a P-channel transistor, wherein off-state current of the first transistor is less than or equal to 1×10−20 A at a temperature of 25° C., wherein the off-state current of the first transistor is less than or equal to 1/100 of leakage current of the display element, and wherein capacitance of the capacitor is less than or equal to 1/10 of capacitance of the display element. |
地址 |
Atsugi-shi, Kanagawa-ken JP |