发明名称 Methods and apparatuses for identifying and alleviating internal bottlenecks prior to processing packets in internal feature modules
摘要 Methods and apparatuses for identifying and alleviating bottlenecks prior to processing packets in internal feature modules are described. First, a method is provided for aggregating the service policies of various physical interfaces, and using results of the aggregation to determine whether a packet processing engine is capable of satisfying the aggregated service policy information. Second, a method and apparatus for applying the aggregated service policy prior to processing in an internal feature module, such as a crypto-engine. Packets on routers/switches are expected to be subjected to certain policies to address resource contention or streamlining/prioritization on outbound interfaces. Internal bottlenecks that a user can neither see nor control may cause packet transmission guarantees to be violated. Encryption is an example of an internal service that adds overhead thereby creating an internal bottleneck. Such internal bottlenecks are cured through intelligent means of pre-processing and pre-application of certain policy rules.
申请公布号 US9065741(B1) 申请公布日期 2015.06.23
申请号 US200310672476 申请日期 2003.09.25
申请人 Cisco Technology, Inc. 发明人 Varanasi Ravi K.;Ganeshithal Ravishankar
分类号 H04L12/801;H04L29/06;H04L12/911;H04L12/863;H04L12/851 主分类号 H04L12/801
代理机构 Hickman Palermo Becker Bingham LLP 代理人 Hickman Palermo Becker Bingham LLP
主权项 1. A method comprising: determining, prior to a shared internal feature module processing a plurality of packets, whether a total bandwidth of the shared internal feature module is sufficient to concurrently meet a plurality of bandwidth requirements at a corresponding plurality of downstream egress interfaces; responsive to determining that the total bandwidth of the shared internal feature module cannot concurrently meet the plurality of bandwidth requirements at the corresponding plurality of downstream egress interfaces, providing a notification that the shared internal feature module cannot concurrently meet the plurality of bandwidth requirements at the corresponding plurality of downstream egress interfaces; wherein the method is performed by at least one device comprising a processor; and wherein the shared internal feature module is a crypto-processor.
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