发明名称 |
Array substrate and method of fabricating the same |
摘要 |
An array substrate includes a substrate; an oxide semiconductor layer on the substrate, the oxide semiconductor layer including an active area and source and drain areas at both sides of the active area; a gate insulating layer and a gate electrode sequentially on the active area of the oxide semiconductor layer; an inter insulating layer on the gate electrode and having first and second semiconductor contact holes that expose the source and drain areas respectively; and source and drain electrodes on the inter insulating layer and contacting the source and drain areas through the first and second semiconductor contact holes, respectively, wherein the first and second semiconductor contact holes are disposed in two regions. |
申请公布号 |
US9064905(B2) |
申请公布日期 |
2015.06.23 |
申请号 |
US201313914773 |
申请日期 |
2013.06.11 |
申请人 |
LG Display Co., Ltd. |
发明人 |
Jeong Ho-Young;Lee Young-Jang;Lee Bok-Young |
分类号 |
H01L29/786;H01L29/66;H01L27/12 |
主分类号 |
H01L29/786 |
代理机构 |
Morgan, Lewis & Bockius LLP |
代理人 |
Morgan, Lewis & Bockius LLP |
主权项 |
1. An array substrate comprising:
a substrate; an oxide semiconductor layer on the substrate, the oxide semiconductor layer including an active area and source and drain areas at both sides of the active area; a gate insulating layer and a gate electrode sequentially on the active area of the oxide semiconductor layer; a gate line on the gate insulating layer along a first direction; an inter insulating layer on the gate electrode and the gate line and having first and second semiconductor contact holes that expose the source and drain areas respectively; source and drain electrodes on the inter insulating layer and contacting the source and drain areas through the first and second semiconductor contact holes, respectively; and a data line on the inter insulating layer along a second direction, the data line crossing the gate line to define plural pixel regions, wherein the first and second semiconductor contact holes are respectively disposed in two pixel regions, and the gate line is located between the first and second semiconductor contact holes. |
地址 |
Seoul KR |