发明名称 Methods for minimizing edge peeling in the manufacturing of BSI chips
摘要 A method includes forming top metal lines over a semiconductor substrate, wherein the semiconductor substrate is a portion of a wafer having a bevel. When the top metal lines are exposed, an etchant is supplied on the bevel, wherein regions of the wafer sprayed with the etchant has an inner defining line forming a first ring having a first diameter. A trimming step is performed to trim an edge portion of the wafer, wherein an edge of a remaining portion of the wafer has a second diameter substantially equal to or smaller than the first diameter.
申请公布号 US9064770(B2) 申请公布日期 2015.06.23
申请号 US201213551457 申请日期 2012.07.17
申请人 Taiwan Semiconductor Manufacturing Company, Ltd. 发明人 Kuo Chun-Ting;Chen Kei-Wei;Wang Ying-Lang;Wei Kuo-Hsiu
分类号 H01L21/02;H01L27/146 主分类号 H01L21/02
代理机构 Slater & Matsil, L.L.P. 代理人 Slater & Matsil, L.L.P.
主权项 1. A method comprising: forming top metal lines over a semiconductor substrate, wherein the semiconductor substrate is a portion of a wafer comprising a bevel; wherein the top metal lines are exposed, supplying an etchant to the bevel, wherein a region of the wafer supplied with the etchant has an inner defining line forming a first ring having a first diameter; and performing a trimming step to trim an edge portion of the wafer, wherein an edge of a remaining portion of the wafer has a second diameter substantially equal to or smaller than the first diameter.
地址 Hsin-Chu TW