| 主权项 |
1. A memory device comprising:
an array of memory cells arranged into a plurality of rows and columns and having a plurality of word lines and a plurality of bit lines passing through the array, the memory cells in each row being activated via a word line signal on the corresponding word line, and the memory cells in each column being coupled to an associated at least one bit line via which data is written into an activated memory cell of the column during a write operation and data is read from an activated memory cell of the column during a read operation; control circuitry configured to control signals supplied to the word lines and bit lines of the array in order to control said write operation and said read operation; a dummy column of dummy memory cells associated with said array, said dummy column including at least one dummy bit line to which said dummy memory cells are connected, the dummy memory cells including a plurality of loading dummy memory cells for providing a load to said at least one dummy bit line, and at least one write timing dummy memory cell coupled to a dummy word line; dummy write driver circuitry coupled to said at least one dummy bit line; the control circuitry being configured, during said write operation, to activate each of said at least one write timing dummy memory cell via the dummy word line, and to cause the dummy write driver circuitry to control a voltage on the at least one dummy bit line so as to cause a state flip condition to occur within said at least one write timing dummy memory cell; and write detection circuitry configured, on occurrence of the state flip condition, to issue a write terminate signal to the control circuitry to terminate the write operation. |
