发明名称 Semiconductor devices and methods for manufacturing the same
摘要 Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, a method includes forming a first shielding layer on a substrate. The method further includes forming one of source and drain regions, which is stressed, with the first shielding layer as a mask. The method further includes forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask. The method further includes removing a portion of the second shielding layer which is next to the other of the source and drain regions. The method further includes forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of a remaining portion of the second shielding layer.
申请公布号 US9064954(B2) 申请公布日期 2015.06.23
申请号 US201213623567 申请日期 2012.09.20
申请人 Institute of Microelectronics, Chinese Academy of Sciences 发明人 Zhu Huilong;Liang Qingqing;Zhong Huicai
分类号 H01L29/78;H01L29/66;H01L29/165 主分类号 H01L29/78
代理机构 Knobbe Martens Olson & Bear LLP 代理人 Knobbe Martens Olson & Bear LLP
主权项 1. A semiconductor device, comprising: a substrate; and source and drain regions and a gate stack formed on the substrate, wherein the gate stack comprises: a gate dielectric layer; anda gate conductor, which is formed as a spacer on a sidewall of a dielectric layer or a gate spacer on one side of the gate stack, wherein the gate conductor has a first sidewall on the one side and a bottom surface thereof covered by the gate dielectric layer, and a second sidewall opposite to the first sidewall covered by a further dielectric layer different from the gate dielectric layer, wherein one of the source and drain regions is on the same side as the first sidewall with respect to the gate stack and another of the source and drain regions is on the same side as the second sidewall with respect to the gate stack, wherein the gate conductor faces a channel region defined between the source and drain regions via the gate dielectric layer on the bottom surface thereof, and wherein the one of the source and drain regions on the one side of the gate stack is stressed.
地址 Beijing CN