Semiconductor device and method for manufacturing semiconductor device

摘要

To provide a miniaturized transistor having favorable electric characteristics. An oxide semiconductor layer is formed to cover a source electrode layer and a drain electrode layer, and then regions of the oxide semiconductor layer which overlap with the source electrode layer and the drain electrode layer are removed by polishing. Precise processing can be performed accurately because an etching step using a resist mask is not performed in the step of removing the regions of the oxide semiconductor layer overlapping with the source electrode layer and the drain electrode layer. Further, a sidewall layer having conductivity is provided on a side surface of a gate electrode layer in a channel length direction; thus, the sidewall layer having conductivity overlaps with the source electrode layer or the drain electrode layer with a gate insulating layer provided therebetween, and a transistor substantially including an Lov region is provided.

主权项

1. A method for manufacturing a semiconductor device, comprising the steps of:
forming a source electrode layer and a drain electrode layer; forming an oxide semiconductor layer between the source electrode layer and the drain electrode layer; forming a gate insulating layer over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; forming a gate electrode layer over the oxide semiconductor layer; introducing an impurity into the oxide semiconductor layer using the gate electrode layer as a mask to form a first impurity region and a second impurity region in the oxide semiconductor layer; and forming a first conductive sidewall layer and a second conductive sidewall layer with the gate electrode layer therebetween, wherein a length of an upper surface of the oxide semiconductor layer is longer than a length of a lower surface of the oxide semiconductor layer, wherein at least part of the first conductive sidewall layer overlaps with the source electrode layer with the gate insulating layer therebetween, and wherein at least part of the second conductive sidewall layer overlaps with the drain electrode layer with the gate insulating layer therebetween.