发明名称 |
Vertical memory devices and methods of manufacturing the same |
摘要 |
Methods of fabricating vertical memory devices are provided including forming a plurality of alternating insulating layers and sacrificial layers on a substrate; patterning and etching the plurality of insulating layer and sacrificial layers to define an opening that exposes at least a portion of a surface of the substrate; forming a charge trapping pattern and a tunnel insulating pattern on a side wall of the opening; forming a channel layer on the tunnel insulating layer on the sidewall of the opening, the channel layer including N-type impurity doped polysilicon; forming a buried insulating pattern on the channel layer in the opening; and forming a blocking dielectric layer and a control gate on the charge trapping pattern of one side wall of the channel layer. |
申请公布号 |
US9064895(B2) |
申请公布日期 |
2015.06.23 |
申请号 |
US201313943911 |
申请日期 |
2013.07.17 |
申请人 |
Samsung Electronics Co., Ltd. |
发明人 |
Kim Bi-O;Nakanishi Toshiro;Noh Jin-Tae;Sun Chang-Woo;Lim Seung-Hyun;Ahn Jae-Young;Hwang Ki-Hyun |
分类号 |
H01L27/115;H01L29/66;H01L21/8239;H01L29/788;H01L29/792 |
主分类号 |
H01L27/115 |
代理机构 |
Myers Bigel Sibley & Sajovec |
代理人 |
Myers Bigel Sibley & Sajovec |
主权项 |
1. A method of fabricating a vertical memory device, comprising:
forming a plurality of alternating insulating layers and sacrificial layers on a substrate; patterning and etching the plurality of insulating layer and sacrificial layers to define an opening that exposes at least a portion of a surface of the substrate; forming a charge trapping pattern and a tunnel insulating pattern on a side wall of the opening; forming a channel layer on the tunnel insulating layer on the sidewall of the opening, the channel layer including N-type impurity doped polysilicon; forming a buried insulating pattern on the channel layer in the opening; and forming a blocking dielectric layer and a control gate on the charge trapping pattern of one side wall of the channel layer, wherein the forming of the channel layer comprises: forming an undoped amorphous silicon layer on the tunnel insulating pattern; implanting N-type impurities into the undoped amorphous silicon layer to provide a doped amorphous silicon layer; crystallizing the doped amorphous silicon layer to form a polysilicon layer; and partially etching the polysilicon layer provide the channel layer. |
地址 |
KR |