Array substrate for liquid crystal display having gate line, gate electrode and data pattern in at least two trenches and method of fabricating the same

摘要

An array substrate includes: a trench having a depth from a surface of a substrate; a gate line, a gate electrode and a data pattern filling the respective trenches, wherein the data pattern is between the adjacent gate lines; a gate insulating layer on the gate line, the gate electrode and the data pattern, substantially flat over the substrate, and including contact holes that expose both ends of the data pattern, respectively; a data connection portion on the gate insulating layer and contacting the adjacent data patterns through the contact holes; a source electrode extending from the data connection portion, and a drain electrode spaced apart from the source electrode; a passivation layer on the source and drain electrodes and including a drain contact hole exposing the drain electrode; and a pixel electrode on the passivation layer and contacting the drain electrode through the drain contact hole.

主权项

1. An array substrate comprising:
a substrate including a pixel region; trenches formed in the substrate and having a depth from a surface of the substrate; a gate line, a gate electrode and a data pattern filling at least two of the trenches, wherein the data pattern is between adjacent gate lines; a gate insulating layer on the gate line, the gate electrode and the data pattern, substantially flat over the substrate, and including contact holes that expose ends of the data pattern; a semiconductor layer on the gate insulating layer over the gate electrode; a data connection portion on the gate insulating layer and contacting adjacent data patterns through the contact holes; a source electrode connected to the data connection portion, and a drain electrode spaced apart from the source electrode; a pixel electrode connected to the drain electrode; and a passivation layer on the source and drain electrodes and including a drain contact hole exposing the drain electrode, wherein the pixel electrode is on the passivation layer and contacts the drain electrode through the drain contact hole, and wherein the source electrode extends from the data connection portion and on the semiconductor layer.