Cavity based packaging for MEMS devices

摘要

A wafer structure (88) includes a device wafer (20) and a cap wafer (60). Semiconductor dies (22) on the device wafer (20) each include a microelectronic device (26) and terminal elements (28, 30). Barriers (36, 52) are positioned in inactive regions (32, 50) of the device wafer (20). The cap wafer (60) is coupled to the device wafer (20) and covers the semiconductor dies (22). Portions (72) of the cap wafer (60) are removed to expose the terminal elements (28, 30). The barriers (36, 52) may be taller than the elements (28, 30) and function to prevent the portions (72) from contacting the terminal elements (28, 30) when the portions (72) are removed. The wafer structure (88) is singulated to form multiple semiconductor devices (89), each device (89) including the microelectronic device (26) covered by a section of the cap wafer (60) and terminal elements (28, 30) exposed from the cap wafer (60).

主权项

1. A semiconductor device comprising: a device wafer portion having a first set of inactive regions and a second inactive region; a semiconductor die positioned on a side of said device wafer portion, said semiconductor die including a microelectronic device and multiple conductive lines in physical and electrical contact with said microelectronic device, wherein each inactive region of said first set of inactive regions is located between every two adjacent conductive lines of said semiconductor die; bond pads, one each of said bond pads being in electrical communication with one each of said multiple conductive lines, wherein said bond pads are adjacent to said second inactive region; a first set of barriers positioned in said first set of inactive regions by having one barrier of said first set of barriers in each of said inactive regions of said first set of inactive regions, wherein said barriers do not contact said multiple conductive lines; a second barrier positioned in said second active region; and a cap wafer section coupled to said device wafer portion and covering said microelectronic device, said cap wafer section not covering said bond pads such that said bond pads are exposed.