Phase adjustment scheme for time-interleaved ADCS

摘要

Methods and apparatuses are described for versatile phase adjustment schemes comprising multi-layered clock skew correction with variable range and resolution to improve performance for a variety of ADC architectures, including TI-ADCs. Multi-stage phase alignment corrects misalignment in multiple stages at start-up and continuously or periodically during operation to reduce static sources of misalignment caused by design and fabrication and dynamic sources of misalignment caused by operational variations (e.g., voltage, temperature). Multi-path phase alignment corrects misalignment in the data path (e.g., analog path) and the clock path (e.g., digital path, analog path, CMOS path, CML path, or any combination thereof) for distributed alignment. Multi-lane phase alignment corrects misalignment in multiple time-interleaved signal lanes. Multi-resolution phase alignment corrects misalignment at three or more levels of resolution (e.g., coarse, fine and ultra-fine). Multi-type phase alignment corrects misalignment using different techniques (e.g., controlled current, resistance, capacitance) in a suitable path.

主权项

1. A device comprising:
a clock path having a clock path timing calibration circuit that comprises:
a first calibration circuit having a first timing resolution; anda second calibration circuit having a second timing resolution; a data path having a data path timing calibration circuit that comprises:
a third calibration circuit having a third timing resolution; and coordinated control of the data path timing circuit and the clock path timing circuit to calibrate timing of the device; wherein the first, second and third resolutions are different.