| 摘要 |
PROBLEM TO BE SOLVED: To relax the layout limit of metal wiring to be connected with vertical transistors formed while being arranged. ! SOLUTION: A semiconductor device 100 includes active regions 1A, 1B arranged on one side of a semiconductor substrate and an element isolation region 2 surrounding the periphery thereof, first wiring arranged above the active regions, a lower diffusion layer arranged in the active regions, embedded wiring 45 arranged to extend from the lower diffusion layer to the element isolation region, and second wiring arranged above the embedded wiring in the same layer as the first wiring, and connected with the lower diffusion layer via the embedded wiring. ! COPYRIGHT: (C)2015,JPO&INPIT |
