DEVICE HAVING MULTIPLE-LAYER PINS IN MEMORY MUX1 LAYOUT

摘要

An integrated circuit (IC) memory device comprises a first conductive layer; a second conductive layer formed on the first conductive layer, and electrically connected to the first conductive layer; a third conductive layer formed on the second conductive layer, and separate from the second conductive layer; a fourth conductive layer formed on the third conductive layer, and electrically connected to the third conductive layer; and a 2P2E pin box formed in the first conductive layer or the second conductive layer, and electrically connected to the first conductive layer or the second conductive layer; and an 1P1E pin box formed in the third conductive layer or the fourth conductive layer, and electrically connected to the third conductive layer or the fourth conductive layer.