发明名称 |
METHOD AND APPARATUS FOR VALIDATING A TEST PATTERN |
摘要 |
A method and apparatus of validating a test pattern for at-speed testing of at least one integrated circuit, IC, design. The method comprises calculating at least one weighted rise activity, WRA, value for at least one region of the IC design based at least partly on rising gate transitions within the at least one region of the IC design when the test pattern is applied thereto, calculating at least one weighted fall activity, WFA, value for the at least one region of the IC design based at least partly on fall gate transitions within the at least one region of the IC design when the test pattern is applied thereto, and validating the test pattern based at least partly on the WRA value and the WFA value. |
申请公布号 |
WO2015087114(A1) |
申请公布日期 |
2015.06.18 |
申请号 |
WO2013IB60928 |
申请日期 |
2013.12.13 |
申请人 |
FREESCALE SEMICONDUCTOR, INC.;MILLER, YOAV;BERKOVITZ, ASHER;SOFER, SERGEY |
发明人 |
MILLER, YOAV;BERKOVITZ, ASHER;SOFER, SERGEY |
分类号 |
G01R31/28 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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