发明名称 Load-Through Fault Mechanism
摘要 A mechanism is provided for accessing data in a hybrid hardware managed cache in front of flash memory enabling load/store byte addressability to flash memory. A determination is made as to whether a real address associated with the effective address associated with a request resides in a page table. Responsive to the real address existing in the page table, responsive to the real address referring to a flash page, and, responsive to the flash page failing to reside in the hybrid hardware managed cache, a load-through fault is issued that allows the faulting processor executing the request to execute other work while the flash page is brought into the hybrid hardware managed cache. The operation is then issued to the new hybrid hardware managed cache real address.
申请公布号 US2015169464(A1) 申请公布日期 2015.06.18
申请号 US201314104026 申请日期 2013.12.12
申请人 International Business Machines Corporation 发明人 Swanberg Randal C.
分类号 G06F12/10;G06F12/12 主分类号 G06F12/10
代理机构 代理人
主权项
地址 Armonk NY US