VOLTAGE REGULATOR

摘要

Provided is a voltage regulator configured to suppress overshoot and undershoot so as to output a stabilized voltage. The voltage regulator includes: a high pass filter configured to detect a fluctuation in power supply voltage; a high pass filter configured to detect a fluctuation in output voltage; transistors connected in series, which are each configured to cause a current to flow in accordance with an output of corresponding one of the high pass filters; and a clamp circuit configured to clamp a drain voltage of one of the transistors connected in series. The voltage regulator controls a gate voltage of an output transistor based on a drain voltage of a transistor that includes a gate controlled by the drain voltage of the one of the transistors connected in series.

主权项

1. A voltage regulator configured to stabilize a power supply voltage input from a power supply terminal to output the stabilized power supply voltage, the voltage regulator comprising:
an output transistor configured to output an output voltage; an error amplifier circuit configured to amplify a difference between a divide voltage obtained by dividing the output voltage and a reference voltage to output the amplified difference, thereby controlling a gate of the output transistor; a first high pass filter configured to detect a fluctuation in the power supply voltage; a second high pass filter configured to detect a fluctuation in the output voltage; a first transistor configured to cause a current to flow in accordance with an output voltage of one of the first high pass filter and the second high pass filter; a second transistor connected in series to the first transistor, the second transistor being configured to cause a current to flow in accordance with an output voltage of another one of the second high pass filter and the first high pass filter; a clamp circuit configured to clamp a drain voltage of the first transistor; and a third transistor including a gate connected to a drain of the first transistor and a drain connected to the gate of the output transistor, the third transistor being configured to control an operation of the output transistor based on the drain voltage of the first transistor.