发明名称 VECTOR FUNCTIONAL UNIT, METHOD, AND COMPUTING SYSTEM
摘要 PROBLEM TO BE SOLVED: To provide a vector functional unit mounted on a semiconductor chip so as to execute an N-dimensional vector operation.SOLUTION: A vector functional unit includes: N functional units each of which includes a logic circuit; and a masking circuit that causes an output result to be presented from one that is selected out of the N functional units. Each of the logic circuits executes: a first integer multiply add instruction that presents a bit part on the most significant side of a first integer multiply add calculation but does not present a bit part on the least significant side; a second integer multiply add instruction that presents a bit part on the least significant side of a second integer multiply add calculation but does not present a bit part on the most significant side; and a floating-point multiply add instruction.
申请公布号 JP2015111421(A) 申请公布日期 2015.06.18
申请号 JP20140256542 申请日期 2014.12.18
申请人 INTEL CORP 发明人 JEFF WIEDEMEIER;SRIDHAR SAMUDRALA;ROGER GOLLIVER
分类号 G06F9/305;G06F7/00;G06F7/575;G06F9/38 主分类号 G06F9/305
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