METHOD FOR REDUCING CORE-TO-CORE MISMATCHES IN SOC APPLICATIONS

摘要

Methods for reducing core-to-core mismatch are provided. The method includes measuring gate lengths of a representative pattern of each core in a first lot of SOC products by a measurement apparatus. Each of the SOC products in the first lot includes more than two cores identical to each other. The method also includes determining tuning amounts according to the differences between the gate lengths of each core, and adjusting manufacturing conditions for critical dimensions of gate length of each core in a second lot of SOC products respectively according to the tuning amounts for reducing core-to-core mismatch due to the surrounding environment of each core. Each of the SOC products in the second lot includes more than two cores identical to each other and also identical to the core in the first lot.

主权项

1. A method for reducing core-to-core mismatch, comprising:
measuring gate lengths of a representative pattern of each core in a first lot of system-on-chip (SOC) products by a measurement apparatus, wherein each of the SOC products in the first lot includes more than two cores identical to each other; determining a tuning amount according to the differences between the gate lengths of each core; and adjusting manufacturing conditions for critical dimensions (CDs) of gate length of each core in a second lot of SOC products respectively according to the tuning amounts for reducing core-to-core mismatch due to the surrounding environment of each core, wherein each of the SOC products in the second lot includes more than two cores identical to each other and also identical to the core in the first lot.